The present invention relates to improvements in a memory device with a register interchange function for use in a data processor.
In a microprocessor, one of the fundamental operations of data processing is the interchange of data stored in a memory device such as a register.
A basic arrangement of a conventional memory device configuration requiring such data interchange is shown in FIG. 1.
In FIG. 1, reference numeral 1 designates a register file comprising n registers R0-Rn-1. One of the registers R in the register file 1 is selected by a register select circuit 2. Select data Sj (j=0, 1, 2, . . . m) of (m+1) bits is stored in the register select circuit 2. A combination of the select data Sj, or the bit information, selects one of the select signals SRi (i=0, 1, 2, . . . , n-1). Then, the select signal SRi specifies a corresponding register Ri.
An input/output (I/O) control unit 3 controls data input and output to and from the selected register R. The I/O control unit 3 is connected to a data bus 4 for providing a common path to transfer various types of data.
A temporary register file 5 comprises a couple of temporary registers TM0 and TM1. An input/output control unit 6, provided between the temporary register file 5 and the data bus 4, is for the temporary register file 5.
In the above memory device, data is interchanged between the register R1 and Rn-1, for example, in the following way. To start, the register R1 is selected by the register select circuit 2, and the contents of the register R1 are temporarily stored in the register TM0 in the temporary register file 5 through the I/O unit 3, the data bus 4 and the I/O unit 6. Similarly, the register Rn-1 is selected and the contents thereof are temporarily stored in the register TM1 in the temporary register file 5. Then, through the same path in the reverse direction, i.e., the I/O unit 6, the data bus 4 and the I/O unit 3, the contents in the register TM1 are loaded into the register R1. Finally, the register TM0 is selected, and the contents thereof are loaded into the register Rn-1. The above operations are summarized in the following. EQU R1.fwdarw.TM0 EQU Rn-1.fwdarw.TM1 EQU TM1.fwdarw.R1 EQU TM0.fwdarw.Rn-1
In a system including an accumulator, either of the temporary registers TM0 and TM1 may also serve as an accumulator.
As described above, the conventional memory device requires two extra registers for data interchange, in addition to the register file. Further, the conventional memory device requires at least four operations for transferring data between the registers. As a result, the memory device has a complicated circuit arrangement, and the data interchange takes a long time.